I have finally found long waiting opportunity and time to fulfill long tabled project of video graphics adapter. The initial thought was to implement the adapter entirely using TTL-series chips. Being big fan of homebrew S100 computer series (s100computers.com) it was obvious choice to design new graphics adapter to support DYI build by more but also les experienced enthusiast from which most prefer through hole pcb assembly.
I started from block diagram of the first out of main three subsystems present in every old and modern graphics adapter, these are:
- picture synchronization block
- frame buffer
Next, was the capturing the design into schematic diagram using standard TTL-Series components. This became a large task initially when I assumed the fram buffer will be made using external RAM. Double buffering standard single port SRAM chip requires lots of TTL-chips and dual-port RAMs are rare and expensive.
With that completed I wanted to verify the design and one logical choice before building the prototype was to simulate the logic circuit I designed.
After extensive research and trials of several free, shareware and paid/trial simulators I ended up with simulator available from one of major fpga manufacturers Intel/Altera. It contained all the libraries I needed to port my schematic based design into the simulation. The result of the verification was positive, my synchronization block was working as expected producing horizontal and vertical synchronization signals as well as address to each pixel contained with then picture frame.
Now it was time to add frame buffer. This was task behind simulation, so I had to think about building actual circuit. When I counter number of required TTL-chips at this early stage of the design it turned to be over 20. The number of connections I would have to do on the breadboard would exceed 500, therefore I decided to skip the TTL-based prototype design and use results from my simulation to port this design into existing off the shelf fpga chip. The cost of evaluation kit with suitable fpga chip turned to be under $50 which was great plus no prototyping and wiring would be necessary.
I tailored my fpga based circuit to eliminate any external connections except those to hook up DB15HD VGA output to connect with VGA monitor. Thanks for embedded into fpga Flash, I was also able to load and display generic picture (in graphics mode) and boot text (in text mode) to validate my design to ensure it works and displays correct content.
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Below are renders of the ISA version of the VGA51 card with dual monitor capablity. Depopulating 2nd DB15 socket and relevant discrette resistors would downgrade this card to single monitor only.
The VGA51 fpga is placed on dedicated mezzanine adapter. This way the base board remains through hole which makes it easy to be assembled at home by anyone who has basic soldering knowledge.
Also, the use of mezzanine allows to test ISA card with different fpga's to enable future card extensions and functionality with graphic modes up to full high definition and 4K. Yes, the existing fpga chips enable all these easily.
The mezzanine board houses also required decopling capacitors. There are 50 of those and all needed to ensure compliance or at least minimalization of the electromagnetic emissions (EMI) which can affect other wireless networks in and around the household. Optional surface mount oscillator enables its use when needed with higher driving frequencies comparing to when used on the base board due to much shorter connection between oscillator output and fpga clock input.
Currently an ISA version (shown above) of the VGA51 board is being fabricated. The PC platfom is a great way to benchmark the design hence the choice. Once the ISA version is brough up and proven to meet the specificaiton of control as well as capabilities, I plan to migrate this design to interface with S100 platform. I have been colleting valuable opinions from S100 Computer Google Group members also sharing vga51 design progress there. O also want to give lot of credit to s100computers.com dedicated website and its author for great feedback and samples of s100 boards John designed and described there.
For the S100 version of the VGA51 adapter, I am also building my own s100 computer and I capture its progress on this website in separate section.
And pictures of the screen generared by VGA51 for two implemented text modes:
80x25 (uses 640x400 physical screen resolution)
80x30 (uses 640x480 physical screen resolution) - note message on the bttom of the screen I wrote into video RAM address corresponding with line 30th of the text:
Close up on the text to compare both test modes. The 80x25 (based on 640x400 resoltion) was standard for DOS programs and is often seen during PC boot when BIOS displays diagnostic progress.
In above examples I used CRT monitor to asses the screen "look and feel" compatiblity with old PC's and it replicates it perfectly. With the identical resolution of the screen and same font bitmap why shouldn't it? The newer LCD monitors and TV are handling both resolutions without a problem showing same screen just with "smoother" fonts where no dark lines are seen between each font bitmap row - see below:
The graphic mode (320x200) screen example is shown below, it is just simple color bar screen which I generated using binary editor and initiated video RAM with it.
The OSD text in the center comes form monitor to display picture properties.
Below is also the picture of dual screen mode generating individual text and graphic test screen on two connected monitors.
Next I plan to generate few pictures and load these into video ram in graphics mode.
In the meantime, take a look at this Youtube video showing all three VGA51 modes of operation:
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